FIU Discovery

Thermal-constrained energy efficient real-time scheduling on multi-core platforms.  Parallel Computing.  85:231-242.

M-Oscillating: Performance Maximization on Temperature-Constrained Multi-Core Processors.  IEEE Transactions on Parallel and Distributed Systems.  29:2528-2539.

TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, and Reliability Optimizations.  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.  37:1985-1998.

Efficient LDPC Code Design for Combating Asymmetric Errors in STT-RAM.  ACM Journal on Emerging Technologies in Computing Systems.  14.

Improving AES Core Performance via an Advanced ASBUS Protocol.  ACM Journal on Emerging Technologies in Computing Systems.  14.

An Energy-Efficient GPGPU Register File Architecture Using Racetrack Memory.  IEEE transactions on computers.  66:1478-1490.

Energy-Aware Adaptive Restore Schemes for MLC STT-RAM Cache.  IEEE transactions on computers.  66:786-798.

A Fault-Tolerant Neural Network Architecture

Deep-Evasion: Turn Deep Neural Network into Evasive Self-Contained Cyber-Physical Malware.  320-321.

E-RNN: Design Optimization for Efficient Recurrent Neural Networks in FPGAs.  IEEE Symposium on High-Performance Computer Architecture (HPCA). 69-80.

Game Theoretic-based Approaches for Cybersecurity-aware Virtual Machine Placement in Public Cloud Clusters.  2017 17TH IEEE/ACM INTERNATIONAL SYMPOSIUM ON CLUSTER, CLOUD AND GRID COMPUTING (CCGRID). 272-281.

Universal Approximation Property and Equivalence of Stochastic Computing-Based Neural Networks and Binary Neural Networks.  THIRTY-NINTH AAAI CONFERENCE ON ARTIFICIAL INTELLIGENCE, AAAI-25, VOL 39 NO 27. 5369-5376.

An ECC-Free MLC STT-RAM based Approximate Memory Design for Multimedia Applications.  Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI. 142-147.

DeepN-JPEG: A Deep Neural Network Favorable JPEG-based Image Compression Framework.  Proceedings - Design Automation Conference.

Enhancing the Robustness of Deep Neural Networks from "Smart" Compression.  Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI. 528-532.

PT-Spike: A Precise-Time-Dependent Single Spike Neuromorphic Architecture with Efficient Supervised Learning.  2012 17TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC). 568-573.

SIN²: Stealth Infection on Neural Network - A Low-cost Agile Neural Trojan Attack Methodology.  227-230.

Security Analysis and Enhancement of Model Compressed Deep Learning Systems under Adversarial Attacks.  2012 17TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC). 721-726.

Special Session on Reliability and Vulnerability of Neuromorphic Computing Systems.  2018 IEEE 36TH VLSI TEST SYMPOSIUM (VTS 2018).

Understanding Adversarial Attack and Defense towards Deep Compressed Neural Networks.  Proceedings of SPIE - The International Society for Optical Engineering.

A Fast and Ultra Low Power Time-based Spiking Neuromorphic Architecture for Embedded Applications.  ISQED 2009: PROCEEDINGS 10TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, VOLS 1 AND 2. 19-22.

A Statistical STT-RAM Retention Model for Fast Memory Subsystem Designs.  2012 17TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC). 720-725.

Algorithm-Hardware Co-Optimization of the Memristor-Based Framework for Solving SOCP and Homogeneous QCQP Problems.  2012 17TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC). 788-793.

Design of A Pre-Scheduled Data Bus for Advanced Encryption Standard Encrypted System-on-Chips.  2012 17TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC). 506-511.

MT-Spike: A Multilayer Time-based Spiking Neuromorphic Architecture with Temporal Error Backpropagation.  IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers. 450-457.

Processor/Memory Co-scheduling Using Periodic Resource Server for Real-Time Systems Under Peak Temperature Constraints.  ISQED 2009: PROCEEDINGS 10TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, VOLS 1 AND 2. 360-366.

XNOR-POP: A Processing-in-Memory Architecture for Binary Convolutional Neural Networks in Wide-I02 DRAMs.  Proceedings of the International Symposium on Low Power Electronics and Design.

A Data Locality-aware Design Framework for Reconfigurable Sparse Matrix-Vector Multiplication Kernel.  IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers.

A Holistic Tri-region MLC STT-RAM Design with Combined Performance, Energy, and Reliability Optimizations.  Proceedings -Design, Automation and Test in Europe, DATE. 1285-1290.

A Novel PUF based on Cell Error Rate Distribution of STT-RAM.  2012 17TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC). 342-347.

AOS: Adaptive Overwrite Scheme for Energy-Efficient MLC STT-RAM Cache.  Proceedings - Design Automation Conference.

Efficient Low-Density Parity-Check (LDPC) Code Decoding for Combating Asymmetric Errors in STT-RAM.  Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI. 266-271.

Hardware Security Challenges Beyond CMOS: Attacks and Remedies.  Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI. 200-205.

Improving Read Performance of STT-MRAM based Main Memories through Smash Read and Flexible Read.  2012 17TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC). 31-36.

NVSim-VX^s: An Improved NVSim for Variation Aware STT-RAM Simulation.  Proceedings - Design Automation Conference.

On Harmonic Fixed-Priority Scheduling of Periodic Real-Time Tasks with Constrained Deadlines.  Proceedings - Design Automation Conference.

Performance Maximization via Frequency Oscillation on Temperature Constrained Multi-core Processors.  2002 INTERNATIONAL CONFERENCE ON PARALLEL PROCESSING, PROCEEDING. 526-535.

Security of Neuromorphic Computing: Thwarting Learning Attacks Using Memristor's Obsolescence Effect.  IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers.

Sliding Basket: An Adaptive ECC Scheme for Runtime Write Failure Suppression of STT-RAM Cache.  Proceedings -Design, Automation and Test in Europe, DATE. 762-767.

Recent Progresses of STT Memory Design and Applications.  Proceedings of International Conference on ASIC.