TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, and Reliability Optimizations Article

Liu, Zihao, Mao, Mengjie, Liu, Tao et al. (2018). TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, and Reliability Optimizations . IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 37(10), 1985-1998. 10.1109/TCAD.2017.2783860

Open Access Industry Collaboration International Collaboration

cited authors

  • Liu, Zihao; Mao, Mengjie; Liu, Tao; Wang, Xue; Wen, Wujie; Chen, Yiran; Li, Hai; Wang, Danghui; Pei, Yukui; Ge, Ning

sustainable development goals

authors

publication date

  • October 1, 2018

webpage

published in

keywords

  • Cache partitioning
  • Computer Science
  • Computer Science, Hardware & Architecture
  • Computer Science, Interdisciplinary Applications
  • Engineering
  • Engineering, Electrical & Electronic
  • LEVEL PERFORMANCE
  • Science & Technology
  • Technology
  • data migration
  • multilevel cell (MLC)
  • nonuniform ECC
  • spin-transfer torque random access memory (STT-RAM)

Digital Object Identifier (DOI)

publisher

  • IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

start page

  • 1985

end page

  • 1998

volume

  • 37

issue

  • 10