IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Journal

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TSLA: A Task-Specific Learning Adaptation for Semantic Segmentation on Autonomous Vehicles Platform. 44:1406-1419. 2025
PATH: Evaluation of Boolean Logic Using Path-Based In-Memory Computing Systems. 43:1387-1400. 2024
STREAM: Toward READ-Based In-Memory Computing for Streaming-Based Processing for Data-Intensive Applications. 42:3854-3867. 2023
COMPACT: Flow-Based Computing on Nanoscale Crossbars With Minimal Semiperimeter and Maximum Dimension. 41:4600-4611. 2022
NASA: NVM-Assisted Secure Deletion for Flash Memory. 41:3779-3790. 2022
XMAP: Programming Memristor Crossbars for Analog Matrix-Vector Multiplication: Toward High Precision Using Representable Matrices. 41:1827-1841. 2022
GC-Steering: GC-Aware Request Steering and Parallel Reconstruction Optimizations for SSD-Based RAIDs. 39:4587-4600. 2020
TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, and Reliability Optimizations. 37:1985-1998. 2018
Temperature-Constrained Feasibility Analysis for Multicore Scheduling. 35:2082-2092. 2016
Library-Based Cell-Size Selection Using Extended Logical Effort. 32:1086-1099. 2013
A unified approach to variable voltage scheduling for nonideal DVS processors. 23:1370-1377. 2004
Finding obstacle-avoiding shortest paths using implicit connection graphs. 15:103-110. 1996
A GENERAL GREEDY CHANNEL ROUTING ALGORITHM. 10:204-211. 1991
Minimal energy fixed-priority scheduling for variable voltage processors 2003

International Standard Serial Number (ISSN)

0278-0070

Electronic International Standard Serial Number (EISSN)

1937-4151