Efficient LDPC Code Design for Combating Asymmetric Errors in STT-RAM

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Efficient LDPC Code Design for Combating Asymmetric Errors in STT-RAM Article

Li, Bohua, Pei, Yukui, Wen, Wujie. (2018). Efficient LDPC Code Design for Combating Asymmetric Errors in STT-RAM . ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, 14(1), 10.1145/3154836

International Collaboration

cited authors

Li, Bohua; Pei, Yukui; Wen, Wujie

sustainable development goals

SDG 11: Sustainable Cities and Communities

authors

Wen, Wujie

publication date

March 1, 2018

webpage

https://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000429195300010&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=e451fd656366bf1ec5554941920a9ccb

published in

ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS Journal

keywords

Computer Science
Computer Science, Hardware & Architecture
DENSITY
Engineering
Engineering, Electrical & Electronic
MRAM
Nanoscience & Nanotechnology
PERFORMANCE
Science & Technology
Science & Technology - Other Topics
Spin-transfer torque random access memory (STT-RAM)
Technology
asymmetric log-likelihood ratio (A-LLR)
channel model
low-density parity-check (LDPC) code
reliability
semi-random parity check matrix

Digital Object Identifier (DOI)

https://doi.org/10.1145/3154836

publisher

ASSOC COMPUTING MACHINERY

volume

14

issue

1