The combined use of algorithms for approximate discrete cosine transform (DCT) with approximate computing is examined toward area-efficient field programmable gate array (FPGA) hardware architectures. The performance of previously reported, multiplierless approximate DCT transforms are explored in the presence of non-exact hardware adders which provide better utilisation of FPGA resources in terms of look-up-tables (LUTs). In the context of 2D image compression, provided examples are demonstrating a 20% LUT reduction in FPGA utilization compared to accurate adders, with a corresponding image quality degradation of 0.6 dB in terms of PSNR. The potential benefit of such area-efficient FPGA hardware designs is explored on 3D (video compression), 4D (static light field compression), and 5D (light field video compression) cases where significant FPGA resource savings are obtained at the cost of marginal degradation of output quality.
