The use of approximate transforms in conjunction with approximate adder hardware is explored towards implementing low-complexity multi-beam antenna arrays. The use of approximate adders is motivated by the efficient look up table (LUT) usage on field programmable gate arrays (FPGA) resulting in better area and time complexities on hardware. 8-beam and 16-beam hardware architectures for multi-beamforming are designed using previously reported 8-point and 16-point spatial approximate-DFT (ADFT) algorithms, respectively, albeit with approximate adders. Designs have been implemented on Xilinx Kintex UltraScale KCU105 FPGA device verifying 31.5% reduction in (FPGA) LUT count and 58.08% improvement in critical path delay with a maximum beam error of 0.6 degrees and maximum peak side lobe level deviation 0.21 dB for the 8-beam case, when compared to ADFT with accurate adders with the same fixed-point word length. Similarly, for the 16-beam case, the use of approximate adders provide 25.39% reduction LUT count in FPGA with a maximum beam error of 0.6 degrees and peak side lobe level 4.5 dB. Operation of the proposed 8-beam and 16-beam hardware designs are also verified with signal-to-interference ratio (SIR) simulations verifying better than 27.84 dB improvement in SIR at the beamformed output.
