Delay time analysis of submicron InP-based HEMT's Article

Kwon, Y, Pavlidis, D. (1996). Delay time analysis of submicron InP-based HEMT's . IEEE TRANSACTIONS ON ELECTRON DEVICES, 43(2), 228-237. 10.1109/16.481722

cited authors

  • Kwon, Y; Pavlidis, D


  • The intrinsic delay time of submicron InP-based HEMT's has been evaluated by coupling the delay time analysis with a 2D Ensemble Monte Carlo simulation. The relationship between the delay time and the transit time is explained. It is shown that the delay time can be quite different from the transit time depending on the velocity modulation. The delay from each segment of the HEMT is calculated to study the distribution of the delay inside the device. The delay from the gate region was the major contributor while that from the drain region was also important. The bias dependence of the delay in each region of the device was calculated to explain the bias dependence of the total intrinsic delay time. The intrinsic delay time increase at low Vgs was due to the increase of Td and TS and the increase at high Vds was due to the increase of Td. As a means of validation, the simulated data have been compared with experimental intrinsic delay time data at various bias points. Good agreement was found over a wide Vgs and Vds range. © 1996 IEEE Publisher Item Identifier S 0018-93S3(96)01074-X.

publication date

  • December 1, 1996

published in

Digital Object Identifier (DOI)

start page

  • 228

end page

  • 237


  • 43


  • 2