Low Overhead Instruction Latency Characterization for NVIDIA GPGPUs Conference

Arafa, Yehia, Badawy, Abdel-Hameed A, Chennupati, Gopinath et al. (2019). Low Overhead Instruction Latency Characterization for NVIDIA GPGPUs . 2017 IEEE HIGH PERFORMANCE EXTREME COMPUTING CONFERENCE (HPEC)

cited authors

  • Arafa, Yehia; Badawy, Abdel-Hameed A; Chennupati, Gopinath; Santhi, Nandakishore; Eidenbenz, Stephan

authors

date/time interval

  • September 24, 2019 -

publication date

  • January 1, 2019

published in

keywords

  • BENCHMARK SUITE
  • Benchmarking
  • CUDA
  • Computer Science
  • Computer Science, Hardware & Architecture
  • Computer Science, Theory & Methods
  • Engineering
  • Engineering, Electrical & Electronic
  • GPGPUs
  • GPU
  • High-Level Optimizations
  • Latency
  • OPENCL
  • PTX
  • Science & Technology
  • Technology
  • Turing
  • Volta

Location

  • MA, Waltham

Conference

  • IEEE High Performance Extreme Computing Conference (HPEC)

publisher

  • IEEE