To scale wideband multi-beam phased arrays without the power and throughput penalties of per-element digitization, chiplet-based analog/hybrid beamforming uses approximate discrete Fourier transform (ADFT) computation as a practical way for multiplierlessly implementing the DFT stage, leaving the overall architecture at a O(N) multiplicative cost. In this approach, sub-array signals are first amplified and downconverted to IF, where only a selected subset of beams are forwarded by the ADFT chiplets to the digital back-end, reducing data rate and power consumption. This paper presents a 1-8 GHz receiver (RX) front-end designed in TSMC 65-nm CMOS process that serves as the RF interface to IF-domain, pre-processing prior to ADFT matrix-vector multiplication. Pre-layout results show a maximum gain of 49.2 dB and a minimum noise figure (NF) of 6.8 dB, which indicate that the proposed RX front-end is a promising building block for scalable wideband multi-beam RX architectures.
