Timing closure remains a critical challenge in modern VLSI design, and post-synthesis logic resynthesis is one approach to address it by transforming gate-level netlists to fix violations. However, existing approaches typically apply transformations in isolation, optimizing gate sizing independently of buffer insertion or threshold-voltage assignment, and most lack physical design-awareness, producing solutions that degrade after placement and routing. We present MARS (Multi-transformation Adaptive ReSynthesis), a framework with three contributions: (1) coordinated application of four transformation types (gate sizing, Vt swapping, buffer insertion, and gate cloning) within a unified optimization loop; (2) physical design-aware optimization through integration with OpenROAD; and (3) an empirical comparison across four configurations (Sizing-only, Sizing+Vt, Sizing+Buffering, and all four combined) on six benchmarks from the MLCAD 2025 resynthesis contest using the ASAP7 7 nm library. Combining all transformations achieves the best or tied-best results on 5 of 6 benchmarks, reducing Total Negative Slack (TNS) by 47%, slew violations by 95%, and capacitive load violations by 54% on average.
