This paper presents a novel digitally-intensive self-interference cancellation (DI-SIC) technique supporting simultaneous transmission and reception. Key to the design approach is the development of a behavioral model of the full-duplex front-end at the digital baseband. An auxiliary transmitter (TX) chain is deployed to transmit the digitally reconstructed leakage signal and perform analog cancellation at the receiver (RX) input to prevent desensitization. The cancellation algorithm is developed on an AMD-Xilinx radio frequency system-on-chip (RFSoC) incorporating gigasample speed data converters and a field programmable gate array (FPGA). The cancellation architecture is implemented on the programmable logic (PL) and the model coefficients are calculated offline in the ARM processor of the SoC. The hardware demonstration employs a reduced number of off-the-shelf analog components that provide an impressive cancellation of 38 dB for a maximum modulation bandwidth of 400 MHz.
