A speed-optimized systolic array processor architecture for spatio-temporal 2-D IIR broadband beam filters Article

Madanayake, HLP Arjuna, Bruton, Leonard T. (2008). A speed-optimized systolic array processor architecture for spatio-temporal 2-D IIR broadband beam filters . IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 55(7), 1953-1966. 10.1109/TCSI.2008.918214

cited authors

  • Madanayake, HLP Arjuna; Bruton, Leonard T

authors

publication date

  • August 1, 2008

published in

keywords

  • 2-D
  • DESIGN
  • Engineering
  • Engineering, Electrical & Electronic
  • FREQUENCY-PLANAR
  • REALIZATION
  • RECURSIVE DIGITAL-FILTERS
  • Science & Technology
  • Technology
  • VLSI
  • array
  • beam
  • broadband
  • digital
  • digital signal processing (DSP)
  • field-programmable gate array (FPGA)
  • filter
  • infinite-impulse response (IIR)
  • plane wave
  • sensors
  • systolic

Digital Object Identifier (DOI)

publisher

  • IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

start page

  • 1953

end page

  • 1966

volume

  • 55

issue

  • 7