A single-chip FPGA architecture for 3D HR broadband spatiotemporal beam plane-wave filters

A single-chip FPGA architecture for 3D HR broadband spatiotemporal beam plane-wave filters Conference

Madanayake, HLPA, Bruton, LT. (2006). A single-chip FPGA architecture for 3D HR broadband spatiotemporal beam plane-wave filters . Proceedings - IEEE International Symposium on Circuits and Systems, 4927-4930. 10.1109/ISCAS.2006.1693736

cited authors

Madanayake, HLPA; Bruton, LT

authors

Madanayake, Arjuna

abstract

A highly-directional FPGA-based broadband beamformer is proposed using a novel 3D HR plane-wave digital filter. This filter acquires the 3D spatio-temporal input signals from a spatiallyrectangular arrays of sensors that is scanned by only one time-multiplexed A/D converter. The proposed architecture employs a novel scanned-array 3D parallel vector-processor (VP), clocked at 80 MHz, and has the potential to achieve real-time broadband plane-wave filtering on a single low-cost integrated circuit at spatial frame-rates of 19 kHz over a 64 by 64 spatial broadband sensor array. © 2006 IEEE.

publication date

January 1, 2006

published in

Proceedings - IEEE International Symposium on Circuits and Systems Journal

Digital Object Identifier (DOI)

https://doi.org/10.1109/iscas.2006.1693736

start page

4927

end page

4930

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