Time-multiplexed systolic-array processors for real-time 2D IIR beam plane-wave filters Conference

Madanayake, HLPA, Bruton, LT. (2007). Time-multiplexed systolic-array processors for real-time 2D IIR beam plane-wave filters . 686-689. 10.1109/MWSCAS.2007.4488672

cited authors

  • Madanayake, HLPA; Bruton, LT

authors

abstract

  • A systolic-array architecture for real-time implementation of M number of independent 2D IIR spatio-temporal frequency-planar beam filters is proposed. The proposed architecture enables M time-multiplexed beam filters to be implemented on hardware using the arithmetic circuit real-estate required for a single beam filter. The architecture is a building block for highly-selective 2D IIR spatio-temporal fan filter banks for real-time broadband plane-wave fan filtering applications in ultrasonic imaging, intermediate-frequency (IF) digital beamforming, directional audio, and sonar imaging. A prototype of the systolic-array for M=4 beam filters is demonstrated using FPGA circuit implementations having W-bit (W=13,14,...,17) finite-precision arithmetic circuits, and is shown to operate in real-time at up to FCLK = 125 MHz on a single Xilinx Virtex-4 sx35 10ff668 device. ©2007 IEEE.

publication date

  • December 1, 2007

Digital Object Identifier (DOI)

start page

  • 686

end page

  • 689