A CMOS Perimeter Gated SPAD Based Digital Silicon Photomultiplier with Asynchronous AER Readout for PET Applications
Conference
Ara Shawkat, MS, McFarlane, N. (2018). A CMOS Perimeter Gated SPAD Based Digital Silicon Photomultiplier with Asynchronous AER Readout for PET Applications
. 10.1109/BIOCAS.2018.8584722
Ara Shawkat, MS, McFarlane, N. (2018). A CMOS Perimeter Gated SPAD Based Digital Silicon Photomultiplier with Asynchronous AER Readout for PET Applications
. 10.1109/BIOCAS.2018.8584722
We present an architecture for a CMOS digital silicon photomultiplier (SiPM) based on an array of perimeter gated single photon avalanche diodes (PGSPADs). The designed digital SiPM is implemented in a standard 0.5 μm 2-poly, 3-metal CMOS process. In addition to preventing premature edge breakdown, PGSPADs have the capability to tune the noise floor, sensitivity, and dynamic range of the device. Each pixel includes data compression schemes and a single analog counter with a compact implementation to improve fill factor (FF). We implement a fully digital asynchronous address event representation (AER) readout. Simulation results show more than a factor of 10 temporal compression with an improvement of 25% in dead time at the microcell level of the pixel. The PGSPAD digital SiPM is designed for PET applications with an array-level dynamic range of 156 dB, and simulated worst case event readout speed of 20 MHz.
