Low cost, high performance, and high reliability 2.5D silicon interposer Conference

Sundaram, V, Chen, Q, Wang, T et al. (2013). Low cost, high performance, and high reliability 2.5D silicon interposer . 342-347. 10.1109/ECTC.2013.6575593

cited authors

  • Sundaram, V; Chen, Q; Wang, T; Lu, H; Suzuki, Y; Smet, V; Kobayashi, M; Pulugurtha, R; Tummala, R

authors

abstract

  • This paper presents the first demonstration of polycrystalline silicon interposers with fine pitch through package vias (TPV), with less than 5μm RDL lithography at 50μm pitch copper microbump assembly. Silicon interposers with through silicon vias (TSV) and back end of line (BEOL) wiring offer compelling benefits for 2.5D and 3D system integration; however, they are limited by high cost and high electrical loss. The polycrystalline Si interposer with 100-200μm thick raw Si, obtained without any back-grind or polish, and double side processing, without the use of carriers, has the potential to reduce the cost of wafer-based Si interposers by 2× and up to 10× by scaling to large panels. Thick polymer liner reduces the electrical loss of TPVs dramatically, by an order of magnitude compared to TSVs with SiO2 liner. Initial reliability of TPVs at 150μm and 200μm pitch was demonstrated with daisy chains passing 1000 thermal cycles from -55°C to 125°C. The paper concludes with Cu-SnAg microbump assembly at 50μm pitch onto panel Si interposers with Cu-polymer RDL routing at 4-5μm line lithography. © 2013 IEEE.

publication date

  • September 9, 2013

Digital Object Identifier (DOI)

International Standard Book Number (ISBN) 13

start page

  • 342

end page

  • 347