FPGA-prototypes of differential-form 2D-IIR systolic-array DSP architectures for multi-beam plane-wave filters Conference

Wijenayake, CK, Madanayake, A, Bruton, LT. (2010). FPGA-prototypes of differential-form 2D-IIR systolic-array DSP architectures for multi-beam plane-wave filters . IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation, 58-63. 10.1109/SIPS.2010.5624763

cited authors

  • Wijenayake, CK; Madanayake, A; Bruton, LT

abstract

  • A low-complexity systolic-array architecture is proposed for obtaining multiple(N) broadband radio-frequency (RF) beams in smart antenna arrays. The N-beam 2D IIR digital filter is based on the concept of 2D passive ladder network resonance, leading to differential-form implementations which are highly-suitable for RF throughput levels. The proposed beamformers are converted to differential-form discrete signal flow graphs, mapped to parallel processing core modules(PPCMs) in a locally interconnected array. A 2-beam example of a 2D IIR frequency-planar beam space-time plane-wave filter is described. A prototype design of the architecture is physically implemented on Xilinx Virtex-4 Sx35-10ff668 FPGA device and verified on-chip using measured 2D impulse response and 2D magnitude frequency response tests using on-FPGA chip hardware in the loop co-simulation. The 2-beam FPGA-based example operates at a clock frequency of 40 MHz, implying a real-time frame-rate of 40 Million frames per second. FPGA prototypes are the first step towards eventualy custom silicon VLSI realizations operating at the full RF clock frequency of 800-3000 MHz. ©2010 IEEE.

authors

publication date

  • December 27, 2010

published in

Digital Object Identifier (DOI)

start page

  • 58

end page

  • 63