A review of 2D/3D iir plane-wave real-time digital filter circuits Conference

Madanayake, A, Bruton, LT. (2005). A review of 2D/3D iir plane-wave real-time digital filter circuits . 2005 1935-1941. 10.1109/CCECE.2005.1557361

cited authors

  • Madanayake, A; Bruton, LT


  • Progress is reviewed on the development of circuits that are well suited for the single-chip VLSI circuit realization of two dimensional (2D) and three dimensional (3D) infinite impulse response (IIR) spatio-temporal real-time digital filters. The distributed parallel processor (DPP) and the scanned-array (SA) vector processor circuit architectures are described. The DPP architecture requires the widely-used synchronously-sampled array of sensor signals and is especially useful for high-throughput applications. The SA architectures employ asynchronously-sampled input signals, require only one time-multiplexed A/D converter and are useful where especially low circuit complexity is required. Extensions of these architectures to elemental pre-distorted (EPD) versions lead to further reductions in circuit complexity. The 2D DPP and 3D SA circuits have been implemented on a single field programmable gate array (FPGA) device and tested on-chip via stepped hardware co-simulation They are useful for selectively filtering plane waves in real-time. © 2005 IEEE.

publication date

  • December 1, 2005

Digital Object Identifier (DOI)

start page

  • 1935

end page

  • 1941


  • 2005