Synthesis and Array Processor Realization of a 2-D IIR Beam Filter for Wireless Applications Article

Joshi, Rimesh M, Madanayake, Arjuna, Adikari, Jithra et al. (2012). Synthesis and Array Processor Realization of a 2-D IIR Beam Filter for Wireless Applications . IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 20(12), 2241-2254. 10.1109/TVLSI.2011.2174167

International Collaboration

cited authors

  • Joshi, Rimesh M; Madanayake, Arjuna; Adikari, Jithra; Bruton, Len T

authors

publication date

  • December 1, 2012

published in

keywords

  • Array processors
  • Computer Science
  • Computer Science, Hardware & Architecture
  • Engineering
  • Engineering, Electrical & Electronic
  • FAN
  • SYSTOLIC ARRAY
  • Science & Technology
  • Technology
  • bit error rate (BER)
  • digital phased array feed (PAF)
  • field-programmable gate array (FPGA)
  • multidimensional digital filters
  • spatial modulation
  • systolic
  • wave-front
  • wireless

Digital Object Identifier (DOI)

publisher

  • IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

start page

  • 2241

end page

  • 2254

volume

  • 20

issue

  • 12