A high performance distributed-parallel-processor architecture for 3D IIR digital filters Conference

Madanayake, A, Bruton, L. (2005). A high performance distributed-parallel-processor architecture for 3D IIR digital filters . 1457-1460. 10.1109/ISCAS.2005.1464873

cited authors

  • Madanayake, A; Bruton, L

authors

date/time interval

  • May 23, 2005 -

publication date

  • January 1, 2005

keywords

  • Engineering
  • Engineering, Electrical & Electronic
  • Science & Technology
  • Technology

Location

  • JAPAN, Kobe

Digital Object Identifier (DOI)

International Standard Book Number (ISBN) 10

Conference

  • IEEE International Symposium on Circuits and Systems (ISCAS)

publisher

  • IEEE

start page

  • 1457

end page

  • 1460