A systolic-array architecture for first-order 4-D IIR frequency-planar digital filters Conference

Wimalagunarathne, R, Madanayake, A, Dansereau, DG et al. (2012). A systolic-array architecture for first-order 4-D IIR frequency-planar digital filters . 3069-3072. 10.1109/ISCAS.2012.6271968

cited authors

  • Wimalagunarathne, R; Madanayake, A; Dansereau, DG; Bruton, LT

authors

abstract

  • A novel parallel semi-systolic semi-scanned array architecture is proposed for the implementation of four-dimensional (4-D) IIR filters. These filters have emerging applications in computed tomography (CT), volumetric ultrasound, and light field processing for computer vision. The proposed architecture can be applied to a broad class of 4-D IIR filters, and we show results for a frequency-planar depth-selective filter. Our implementation is on a Xilinx Virtex-6 xc6vsx315t-3ff1156 FPGA, and is suitable for filtering of a N 1 × N 2 = 4 × 4 aperture light field camera input. Results compare favourably with ideal and FPGA-hardware measured outputs, with an N 1N 2 factor increase in throughput compared to a corresponding fully raster-scanned design clocked at the same clock frequency. © 2012 IEEE.

publication date

  • September 28, 2012

Digital Object Identifier (DOI)

start page

  • 3069

end page

  • 3072