A multiplication-free digital architecture for 16×16 2-D DCT/DST transform for HEVC Conference

Edirisuriya, A, Madanayake, A, Cintra, RJ et al. (2012). A multiplication-free digital architecture for 16×16 2-D DCT/DST transform for HEVC . 10.1109/EEEI.2012.6377050

cited authors

  • Edirisuriya, A; Madanayake, A; Cintra, RJ; Bayer, FM

authors

abstract

  • The discrete cosine transform (DCT) is widely employed in image and video coding applications due to its high energy compaction. In addition to 4×4 and 8×8 transforms utilized in earlier video coding standards, the proposed HEVC standard suggests the use of larger transform sizes including 16 × 16 and 32×32 transforms in order to obtain higher coding gains. Further, it also proposes the use of non-square transform sizes as well as the use of the discrete sine transform (DST) in certain intra-prediction modes. The decision on the type of transform used in a given prediction scenario is dynamically made, to obtain required compression rates. This motivated the proposed digital VLSI architecture for a multitransform engine capable of computing 16×16 approximate 2-D DCT/DST transform, with null multiplicative complexity. The relationship between DCT-II and DST-II is employed to compute both transforms using the same digital core, leading to reductions in both area and power. Closed-form relationship between the 16×16 transform and arbitrary smaller sized transform is presented, enabling the usability of this architecture to compute transforms of size 4 · 2P × 4 · 2q where 0 ≤ p, q ≤ 2. © 2012 IEEE.

publication date

  • December 1, 2012

Digital Object Identifier (DOI)