Multiplierless approximate 4-point DCT VLSI architectures for transform block coding Article

Bayer, FM, Cintra, RJ, Madanayake, A et al. (2013). Multiplierless approximate 4-point DCT VLSI architectures for transform block coding . ELECTRONICS LETTERS, 49(24), 1532-1533. 10.1049/el.2013.1352

Open Access International Collaboration

cited authors

  • Bayer, FM; Cintra, RJ; Madanayake, A; Potluri, US

authors

publication date

  • November 21, 2013

published in

keywords

  • 4A4 approximate-discrete cosine transform
  • CMOS integrated circuits
  • CMOS synthesis
  • Engineering
  • Engineering, Electrical & Electronic
  • IMAGE COMPRESSION
  • Science & Technology
  • Technology
  • Xilinx field programmable gate array devices
  • computational architectures
  • digital video
  • discrete cosine transforms
  • dynamic power consumption
  • field programmable gate arrays
  • frequency 1 GHz
  • frequency 125 MHz
  • multiplierless algorithms
  • multiplierless approximate 4-point DCT VLSI architectures
  • power 120 mW
  • power consumption
  • transform block coding
  • transform coding
  • video coding

Digital Object Identifier (DOI)

publisher

  • INST ENGINEERING TECHNOLOGY-IET

start page

  • 1532

end page

  • 1533

volume

  • 49

issue

  • 24