Precise VLSI Architecture for AI Based 1-D/2-D Daub-6 Wavelet Filter Banks With Low Adder-Count Article

Madishetty, Shiva K, Madanayake, Arjuna, Cintra, Renato J et al. (2014). Precise VLSI Architecture for AI Based 1-D/2-D Daub-6 Wavelet Filter Banks With Low Adder-Count . IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 61(7), 1984-1993. 10.1109/TCSI.2014.2298283

International Collaboration

cited authors

  • Madishetty, Shiva K; Madanayake, Arjuna; Cintra, Renato J; Dimitrov, Vassil S

authors

publication date

  • July 1, 2014

published in

keywords

  • 4-TAP
  • Algebraic integer encoding
  • Daubechies wavelets
  • Engineering
  • Engineering, Electrical & Electronic
  • IMAGE COMPRESSION
  • IMPLEMENTATION
  • Science & Technology
  • TRANSFORMS
  • Technology
  • error-free algorithm
  • subband coding

Digital Object Identifier (DOI)

publisher

  • IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

start page

  • 1984

end page

  • 1993

volume

  • 61

issue

  • 7