Compact two-step parallel modified-signed-digit adder/subtractor based on binary logic operations using electron-trapping devices
Conference
Li, G, Qian, F, Ruan, H et al. (1999). Compact two-step parallel modified-signed-digit adder/subtractor based on binary logic operations using electron-trapping devices
. Proceedings of SPIE - The International Society for Optical Engineering, 3805 30-38.
Li, G, Qian, F, Ruan, H et al. (1999). Compact two-step parallel modified-signed-digit adder/subtractor based on binary logic operations using electron-trapping devices
. Proceedings of SPIE - The International Society for Optical Engineering, 3805 30-38.
A compact two-step modified-signed-digit arithmetic-logic array processor is proposed. When the reference digits are programmed, both addition and subtraction can be performed by the same binary logic operations regardless of the sign of the input digits. The optical implementation and experimental demonstration using an electron-trapping device are shown. Each digit is encoded by a single pixel, and no polarization is included. Any combinational logic can be easily performed without optoelectronic and electro-optic conversions of the intermediate results. The system is compact, general-purpose, simple to align and has a high signal-to-noise ratio.
