Current board technologies fail to meet the stringent requirements of the future high-performance microsystems either due to performance (organic) or cost (A1N, Al 2O 3) related issues. New board materials that can support multiple layers of ultra high-density wiring with small capture pads and low-cost flip chip assembly at finer pitch with reliability are needed. FE modeling was done to lay the guidelines for the material property requirements and to study the solder joint fatigue, board warpage and dielectric stresses during thermal cycling. Modeling results showed that though the Si-matched CTE of board results in low solder joint fatigue, it increases the stresses in the dielectric. In addition, apart from dielectric CTE and strength, the thickness of the build-up dielectric layer is also a vital factor in deciding dielectric reliability. A novel process to manufacture C-SiC composite boards was shown to produce large area thin panels at low cost with the required properties of Si-matched CTE and ultra-high modulus. Test vehicles were fabricated with different dielectrics by assembling flip-chips without underfill on these boards followed by reliability testing using liquid-liquid thermal shock tests and in-situ warpage measurements. Modeling and experimental results indicate that boards with low CTE (2-3 ppm/°C) and high stiffness are key factors to control the solder joint and dielectric reliability. Dielectric cracking was minimized with advanced low CTE, high-strength materials and thinner build-up layers. The C-SiC board with the novel manufacturing process meets the property requirements for high density packaging substrates in addition to being low cost and large area processable making it a promising board substrate material for future high-performance microsystems.
