Recent advances in low CTE and high density system-on-a-package (SOP) substrate with thin film component integration Conference

Sundaram, V, Tummala, R, Wiedenman, B et al. (2006). Recent advances in low CTE and high density system-on-a-package (SOP) substrate with thin film component integration . 2006 1375-1380. 10.1109/ECTC.2006.1645836

cited authors

  • Sundaram, V; Tummala, R; Wiedenman, B; Liu, F; Raj, PM; Abothu, IR; Bhattacharya, S; Varadarajan, M; Bongio, E; Sherwood, W

authors

abstract

  • The Packaging Research Center has been developing next generation system-on-a-package (SOP) technology with digital, RF, optical, and sensor functions integrated in a single package/module. The goal of this effort is to develop a platform substrate technology providing very high wiring density and embedded thin film passive and active components using PWB compatible materials and processes. The latest SOP baseline process test vehicle has been fabricated on novel Si-matched CTE, high modulus C-SiC composite core substrates using 10um thick BCB dielectric films with loss tangent of 0.0008 and dielectric constant of 2.65. A semi-additive plating process has been developed for multilayer microvia build-up using BCB without the use of any vacuum deposition or polishing/CMP processes. PWB and package substrate compatible processes such as plasma surface treatment/desmear and electroless/electrolytic pulse reverse plating was used. The smallest line width and space demonstrated in this paper is 6um with microvia diameters in the 15-30um range. This build-up process has also been developed on medium CTE organic laminates including MCL-E-679F from Hitachi Chemical and PTFE laminates with Cu-Invar-Cu core. Embedded decoupling capacitors with capacitance density of >500nF/cm 2 have been integrated into the build-up layers using sol-gel synthesized BaTiO 3 thin films (200-300nm film thickness) deposited on copper foils and integrated using vacuum lamination and subtractive etch processes. Thin metal alloy resistor films have been integrated into the SOP substrate using two methods; (a) NiCrAlSi thin films (25ohms per square) deposited on copper foils (Gould Electronics) laminated on the build-up layers and two step etch process for resistor definition, and (b) electroless plated Ni-W-P thin films (70 ohms to few Kohms per square) on the BCB dielectric by plasma surface treatment and activation. The electrical design and build-up layer structure along with key materials and processes used in the fabrication of the SOP4 test vehicle will be presented in this paper. Initial results from the high density wiring and embedded thin film components will also be presented. The focus of this paper is on integration of materials, processes and structures in a single package substrate for System-on-a-Package (SOP) implementation. ©2006 IEEE.

publication date

  • December 22, 2006

Digital Object Identifier (DOI)

International Standard Book Number (ISBN) 10

International Standard Book Number (ISBN) 13

start page

  • 1375

end page

  • 1380

volume

  • 2006