New paradigm in IC-package interconnections by reworkable nano-interconnects Conference

Aggarwal, AO, Raj, PM, Abothu, IR et al. (2004). New paradigm in IC-package interconnections by reworkable nano-interconnects . 1 451-460.

cited authors

  • Aggarwal, AO; Raj, PM; Abothu, IR; Sacks, MD; Tay, AAO; Tummala, RR

abstract

  • We propose new IC packaging technologies that have the potential to bring about disruptive innovations in interconnect pitch, best electrical and mechanical properties, low-cost and chip size. Current approaches for chip to package interconnections are limited in terms of either pitch or electrical-mechanical trade-off in properties. For example, lead free solder interconnects fail mechanically as the pitch is brought down from current 200 micron pitch to 20 micron. Compliant leads, on the other hand, solve mechanical reliability but at the expense of electrical performance. Solution-derived materials for reworkablè nano-interconnects can be a viable technology to meet these two challenges. Nano-grained electroplated copper is chosen as the primary interconnect material. Compliancy was addressed by tuning the process to electroplate high-aspect-ratio structures. Reworkability was addressed by a thin, liquid lead-free solder interface between the interconnect and the package. Two approaches, sol-gel and electroless plating were used in this work to deposit these liquid interface films of lead free solders of the order of 50-300 nm. In the sol-gel process, metal-organic polymer solutions were heat-treated in a reducing atmosphere at 300°C to form lead-free solders (Sn-Ag-Cu). In the other approach, lead-free alloy films were deposited from aqueous plating solutions consisting of suitable metal salts and reducing agents. This process was done at temperatures of 45°C. The lead-free solder composition was controlled by altering the plating bath formulation. Lead-free solder films formed from both the above approaches were demonstrated to bond copper pads. Solution-derived nano-solder technology is an attractive, low-cost method for bump-less nano-interconnects and other applications such as MEMS hermetic packaging and compliant interconnect bonding.

publication date

  • December 27, 2004

start page

  • 451

end page

  • 460

volume

  • 1