Ultra-thin and ultra-high I/O density package-on-package (3D Thin PoP) for high bandwidth of smart systems Conference

Kim, SJ, Honrao, C, Raj, PM et al. (2013). Ultra-thin and ultra-high I/O density package-on-package (3D Thin PoP) for high bandwidth of smart systems . 406-411. 10.1109/ECTC.2013.6575603

cited authors

  • Kim, SJ; Honrao, C; Raj, PM; Sundaram, V; Tummala, R

authors

abstract

  • Package-on-package (PoP) technologies used in smart phones and tablets are reaching limits in logic-to-memory bandwidth and in thickness reduction. Advances in PoP including through-mold vias (TMVs) and low-CTE, high-modulus laminate substrates have not been able to overcome the I/O density and thickness limitations to date. To overcome these barriers, two major technologies have been pursued. The first approach is chip-first embedding in organic dielectrics and in fan-out wafer level packages. While this can achieve higher I/O's, they face many challenges that include large-die reliability, intermediate testability for higher yield, thermal dissipation, and new supply-chain model. The second approach to address the need is the so-called wide-I/O logic and memory stacking with through silicon vias (TSVs), which promises highest bandwidth in lowest profile, but is viewed as too complex and costly due to TSV integration in logic IC. Georgia Tech PRC proposes and demonstrates, for the first time, a third approach that is more manufacturable and cost-effective. This is referred to as 3D Thin PoP - a more advanced 3-dimensional POP, - designed to achieve ultra-thin stacked packages in 3D with higher chip-to package and package-to-package I/Os to achieve higher bandwidth. This paper reports a number of breakthrough advances in 3D Thin PoP, thus providing a path to extend PoP. These innovations fall into three areas that include: (a) Ultra-thin, 150μm thick organic substrate with multiple layers of build-up wiring with precision cavities ready for chip assembly, (b) die-to-package Cu-Cu interconnections at 30μm pitch bonded at 160°C, and (c) package-on-package stacking with 50μm interconnect pitch. Low signal losses are achieved by having shorter chip-to-chip I/O's and lower stand-off interconnections. These innovations enable higher bandwidth in 3D Thin PoP by virtue of 8× improvement in I/Os combined with 2-3× reduction in total thickness over current PoP. © 2013 IEEE.

publication date

  • September 9, 2013

Digital Object Identifier (DOI)

International Standard Book Number (ISBN) 13

start page

  • 406

end page

  • 411