Enabling chip-to-substrate all-Cu interconnections: design of engineered bonding interfaces for improved manufacturability and low-temperature bonding Conference

Shahane, Ninad, Mohan, Kashyap, Raj, PM et al. (2017). Enabling chip-to-substrate all-Cu interconnections: design of engineered bonding interfaces for improved manufacturability and low-temperature bonding . 2014 IEEE 64TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 968-975. 10.1109/ECTC.2017.313

International Collaboration

cited authors

  • Shahane, Ninad; Mohan, Kashyap; Raj, PM; Smet, Vanessa; Tummala, Rao; Antoniou, Antonia; Ramos, Gustavo; Taylor, Robin; Kilian, Arnd; Wei, Frank

authors

date/time interval

  • May 30, 2017 -

publication date

  • January 1, 2017

published in

keywords

  • COPPER
  • Cu interconnections
  • DIFFUSION
  • Engineering
  • Engineering, Electrical & Electronic
  • GOLD
  • INTERDIFFUSION
  • JOINTS
  • SILICON
  • Science & Technology
  • THIN-FILMS
  • Technology
  • coarsening etc
  • fine pitch
  • flipchip bonding
  • nanocopper
  • nanoporous Cu
  • planarization
  • sintering
  • surface finish
  • thermocompression

Location

  • FL, Lake Buena Vista

Digital Object Identifier (DOI)

Conference

  • IEEE 67th Electronic Components and Technology Conference (ECTC)

publisher

  • IEEE

start page

  • 968

end page

  • 975