Enabling Chip-to-Substrate All-Cu Interconnections: Design of Engineered Bonding Interfaces for Improved Manufacturability and Low-Temperature Bonding Conference

Shahane, N, Mohan, K, Ramos, G et al. (2017). Enabling Chip-to-Substrate All-Cu Interconnections: Design of Engineered Bonding Interfaces for Improved Manufacturability and Low-Temperature Bonding . 968-975. 10.1109/ECTC.2017.313

cited authors

  • Shahane, N; Mohan, K; Ramos, G; Kilian, A; Taylor, R; Wei, F; Raj, PM; Antoniou, A; Smet, V; Tummala, R

abstract

  • This paper presents the design and implementation of engineered nanoscale bonding interfaces as an effective strategy to improve manufacturability of Cu-Cu bonding to the level where it can, for the first time, be applied to chip-to-substrate (C2S) assembly. All-Cu interconnections are highly sought after to meet the escalating electrical, thermal, and reliability requirements of a wide range of emerging digital and analog systems. Such applications require low-cost processes with bonding temperatures and pressures ideally below 200°C and 20MPa, respectively, far from existing solutions established in wafer-level packaging. GT-PRC and its industry partners address this technology gap through innovative designs of bonding interfaces, introducing: 1) novel ultra-thin surface finish metallurgies applied on Cu bumps and pads to prevent oxidation and achieve low-temperature assembly, 2) low-cost fly-cut planarization technique to lower bonding pressures, and 3) low-modulus nanocopper foam caps to provide tolerance to non-coplanarities, and further reduce bonding temperatures and pressures.

publication date

  • August 1, 2017

Digital Object Identifier (DOI)

International Standard Book Number (ISBN) 13

start page

  • 968

end page

  • 975