Demonstration of Patternable All-Cu Compliant Interconnections with Enhanced Manufacturability in Chip-to-Substrate Applications
Conference
Mohan, K, Shahane, N, Sosa, R et al. (2018). Demonstration of Patternable All-Cu Compliant Interconnections with Enhanced Manufacturability in Chip-to-Substrate Applications
. 2018-May 301-307. 10.1109/ECTC.2018.00053
Mohan, K, Shahane, N, Sosa, R et al. (2018). Demonstration of Patternable All-Cu Compliant Interconnections with Enhanced Manufacturability in Chip-to-Substrate Applications
. 2018-May 301-307. 10.1109/ECTC.2018.00053
Emerging 2.5D and 3D package architectures for next-generation high-performance computing and digital applications require high-performance off-chip interconnections at ultra-fine pitch of less than 20μm. All-Cu interconnections are highly desirable as they have excellent electrical and thermal properties. However, current Cu-Cu fine-pitch bonding technologies have limited manufacturability, require special bonding conditions and are mainly limited to wafer-level packaging. A novel approach to realize all-Cu interconnections for chip-to-substrate assembly, utilizing patternable nanoporous copper (np-Cu) foam caps on copper pillars is presented in this paper. The np-Cu foam caps have low modulus to provide tolerance to non-coplanarities, and have very high surface energy which enables assembly at low-temperatures and pressures. The patterned np-Cu films were fabricated by chemical dealloying of co-electroplated Cu-Zn films, using standard semi-additive processing techniques. The patterned foam films were bonded to bulk-Cu at bonding temperature of 250°C for 30min with an applied pressure of 9MPa. During assembly, the np-Cu foams densified and formed good metallurgical contact with the bulk-Cu to achieve a void-free interface.
