A bipolar chip has been designed which attains 1 mu v/ degree C performance in a FET input amplifier. The central problem in the design of the chip was to arrive at an input stage that would minimize FET drain current mismatch. Accordingly, the takeoff to the second stage was made via n-p-n buffers. Instead of using conventional p-n-p active loads, a p-n-p structure which attains the current multiplication effect of the Darlington connection without the attendant degradation in offset voltage and offset current drift of the Darlington, was designed.
