2 MB Array-Level Demonstration of STT-MRAM Process and Performance Towards L4 Cache Applications Conference

Alzate, JG, Hentges, P, Jahan, R et al. (2019). 2 MB Array-Level Demonstration of STT-MRAM Process and Performance Towards L4 Cache Applications . Technical Digest - International Electron Devices Meeting, 2019-December 10.1109/IEDM19573.2019.8993474

cited authors

  • Alzate, JG; Hentges, P; Jahan, R; Littlejohn, A; Mainuddin, M; Ouellette, D; Pellegren, J; Pramanik, T; Puls, C; Quintero, P; Rahman, T; Arslan, U; Sekhar, M; Sell, B; Seth, M; Smith, AJ; Smith, AK; Wei, L; Wiegand, C; Golonzka, O; Hamzaoglu, F; Bai, P; Brockman, J; Chen, YJ; Das, N; Fischer, K; Ghani, T; Heil, P

abstract

  • In this paper, we discuss array-level MTJ process, performance, and reliability requirements for STT-MRAM operation in an L4 Cache application. We demonstrate 2 MB arrays of scaled-size MTJ devices capable of meeting L4 Cache specifications across all proposed temperatures of operation. The technology achieves ECC-correctable bit fail rates for a 20 ns write time, a 4 ns read time, endurance of 1012 cycles, and retention of 1 second at 110 C. Key to achieving these results is the careful co-optimization of the MTJ stack and etch process to minimize array-level tail failure events.

authors

publication date

  • December 1, 2019

published in

Digital Object Identifier (DOI)

volume

  • 2019-December