Intel PowerVia Technology: Backside Power Delivery for High Density and High-Performance Computing Conference

Hafez, W, Agnihotri, P, Asoro, M et al. (2023). Intel PowerVia Technology: Backside Power Delivery for High Density and High-Performance Computing . Digest of Technical Papers - Symposium on VLSI Technology, 2023-June 10.23919/VLSITechnologyandCir57934.2023.10185208

cited authors

  • Hafez, W; Agnihotri, P; Asoro, M; Aykol, M; Bains, B; Bambery, R; Bapna, M; Barik, A; Chatterjee, A; Chiu, PC; Chu, T; Firby, C; Fischer, K; Fradkin, M; Greve, H; Gupta, A; Haralson, E; Haran, M; Hicks, J; Illa, A; Jang, M; Klopcic, S; Kobrinsky, M; Kuns, B; Lai, HH; Lanni, G; Lee, SH; Lindert, N; Lo, CL; Luo, Y; Malyavanatham, G; Marinkovic, B; Maymon, Y; Nabors, M; Neirynck, J; Packan, P; Paliwal, A; Pantisano, L; Paulson, L; Penmatsa, P; Prasad, C; Puls, C; Rahman, T; Ramaswamy, R; Samant, S; Sell, B; Sethi, K; Shah, F; Shamanna, M; Shang, K; Li, Q; Sibakoti, M; Stoeger, J; Strutt, N; Thirugnanasambandam, R; Tsai, C; Wang, X; Wang, A; Wu, SJ; Xu, Q; Zhong, XH; Natarajan, S

abstract

  • This paper presents a high-yielding backside power delivery (BPD) technology, PowerVia, implemented on Intel 4 finFET process. PowerVia more directly integrates power delivery to the transistor as compared to published buried power rail schemes, enabling additional wiring resources on front side for signal routing. A fabricated E-core with > 90% cell utilization showed > 30% platform voltage droop improvement and 6% frequency benefit compared to a similar design without PowerVia. Transistor performance, reliability, and fault isolation capability is detailed.

authors

publication date

  • January 1, 2023

published in

volume

  • 2023-June