Intel PowerVia Technology: Backside Power Delivery for High Density and High-Performance Computing
Conference
Hafez, W, Agnihotri, P, Asoro, M et al. (2023). Intel PowerVia Technology: Backside Power Delivery for High Density and High-Performance Computing
. 2023-June 10.23919/VLSITechnologyandCir57934.2023.10185208
Hafez, W, Agnihotri, P, Asoro, M et al. (2023). Intel PowerVia Technology: Backside Power Delivery for High Density and High-Performance Computing
. 2023-June 10.23919/VLSITechnologyandCir57934.2023.10185208
This paper presents a high-yielding backside power delivery (BPD) technology, PowerVia, implemented on Intel 4 finFET process. PowerVia more directly integrates power delivery to the transistor as compared to published buried power rail schemes, enabling additional wiring resources on front side for signal routing. A fabricated E-core with > 90% cell utilization showed > 30% platform voltage droop improvement and 6% frequency benefit compared to a similar design without PowerVia. Transistor performance, reliability, and fault isolation capability is detailed.