A 70-MHz 8-bit X 8-bit Parallel Pipelined Multiplier in 2.5-µm CMOS

A 70-MHz 8-bit X 8-bit Parallel Pipelined Multiplier in 2.5-µm CMOS Article

Hatamian, M, Cash, GL. (1986). A 70-MHz 8-bit X 8-bit Parallel Pipelined Multiplier in 2.5-µm CMOS . 21(4), 505-513. 10.1109/JSSC.1986.1052564

In this paper we present a design for an 8-bit×8-bit parallel pipelined multiplier for high-speed digital signal-processing applications. The multiplier is pipelined at the bit level. The first version of this multiplier has been fabricated in 2.5-pm CMOS technology. It has been tested at multiplication rates up to 70 MHz with a power dissipation of less than 250 mW. Clock skew is a major problem encountered in high-speed pipelined architectures. This problem is overcome by the use of a balanced clock distribution network all on metal, and proper use of clock buffers. These issues and the timing simulation of the pipeline design are discussed in detail. Extensions and improvements of this work, aimed at achieving higher performance levels, will be described. One such improvement is the conversion of the two-phase clocking scheme used in the present version to an inherently single-phase clock approach. A design using this approach has been completed and simulated at 75 MHz and is currently being fabricated. © 1986 IEEE