An 85-MHz Fourth-Order Programmable IIR Digital Filter Chip Article

Hatamian, M, Parhi, KK. (1992). An 85-MHz Fourth-Order Programmable IIR Digital Filter Chip . IEEE Journal of Solid-State Circuits, 27(2), 175-183. 10.1109/4.127340

cited authors

  • Hatamian, M; Parhi, KK

abstract

  • This paper describes the design and VLSI implementation of a single-chip 85-MHz fourth-order infinite impulse response (IIR) digital filter chip fabricated in 0.9-μm CMOS technology. The coefficient and input data word lengths of the filter are 10 b each; output data word length is 15 b. The coefficients are fully programmable. The chip can be programmed to implement any IIR filter from first to fourth order or an FIR filter up to 16th order at sample rates up to 85 MHz. A total of seventeen 10 x 10 multiply-add modules are used in this chip. The chip contains 80 000 devices in an active area of 14 mm2. It dissipates 2.2 W at 85-MHz clock rate and performs over 1.5 × 109 multiply-add operations per second. The underlying filtering algorithm, chip architecture, circuit and layout design, speed issues, and test results are described. The results of an E-beam probing experiment on packaged chips at 100-MHz clock rates are also presented and discussed. © 1992 IEEE

authors

publication date

  • January 1, 1992

published in

Digital Object Identifier (DOI)

start page

  • 175

end page

  • 183

volume

  • 27

issue

  • 2