A 10.5-GOPS video encoder chip is described which implements CCITT H.261, P∗64, and MPEG (Motion Picture Experts Group) (P-frame) encoding algorithms (including exhaustive motion estimation) at rates up to 30 frames/s with a resolution of up to 352∗288 pixels per frame (CIF format). The chip accepts input video through either a video bus or a 16-b host bus and produces the final encoded bit stream in its output FIFO. A completely self-contained and glueless interface in this chip makes it possible to directly connect it to industry standard DRAM chips (1 MB) needed for frame store. The block diagram of the encoder chip is shown, and the characteristics of the major modules are listed.
