A 65 MHz 16-tap FIR filter chip with on-chip video delay lines
Conference
Rao, SK, Hatamian, M. (1990). A 65 MHz 16-tap FIR filter chip with on-chip video delay lines
. Proceedings - IEEE International Symposium on Circuits and Systems, 4 3050-3052.
Rao, SK, Hatamian, M. (1990). A 65 MHz 16-tap FIR filter chip with on-chip video delay lines
. Proceedings - IEEE International Symposium on Circuits and Systems, 4 3050-3052.
The VLSI design of a 16-tap finite impulse response (FIR) filter chip with programmable line delays for video applications is described. The chip is fabricated in 0.9-μm CMOS technology. It is tested at sample rates up to 65 MHz. The chip contains about 600,000 devices in less than 22 mm2 of silicon area.
