A 65 MHz 16-tap FIR filter chip with on-chip video delay lines Conference

Rao, SK, Hatamian, M. (1990). A 65 MHz 16-tap FIR filter chip with on-chip video delay lines . 4 3050-3052.

cited authors

  • Rao, SK; Hatamian, M

authors

abstract

  • The VLSI design of a 16-tap finite impulse response (FIR) filter chip with programmable line delays for video applications is described. The chip is fabricated in 0.9-μm CMOS technology. It is tested at sample rates up to 65 MHz. The chip contains about 600,000 devices in less than 22 mm2 of silicon area.

publication date

  • December 1, 1990

start page

  • 3050

end page

  • 3052

volume

  • 4