A fast synchronous pipelined CMOS static random access memory (SRAM) capable of reading and writing a new address every 10 ns is described. The design incorporates several interesting techniques-in particular, a novel sense amplifier based on a critically balanced cross-coupled inverter, and associated self-timed read/write logic. A 64-kbit block has been fabricated in the 0.9-mu m digital CMOS process, and tested with a cycle time of better than 10 ns. A 256-kbit version is being designed.
