Standby Power Reduction and SRAM Cell Optimization for 65nm Technology Conference

Lakshminarayanan, S, Joung, J, Narasimhan, G et al. (2009). Standby Power Reduction and SRAM Cell Optimization for 65nm Technology . PROCEEDINGS OF THE SEVENTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN ISQED 2016, 471-+. 10.1109/ISQED.2009.4810340

Industry Collaboration International Collaboration

cited authors

  • Lakshminarayanan, S; Joung, J; Narasimhan, G; Kapre, R; Slanina, M; Tung, J; Whately, M; Hou, C-L; Liao, W-J; Lin, S-C; Ma, P-G; Fan, C-W; Hsieh, M-C; Liu, F-C; Yeh, K-L; Tseng, W-C; Lu, SW

authors

date/time interval

  • March 16, 2009 -

publication date

  • January 1, 2009

webpage

published in

keywords

  • Automation & Control Systems
  • Engineering
  • Engineering, Electrical & Electronic
  • Nanoscience & Nanotechnology
  • SRAM
  • Science & Technology
  • Science & Technology - Other Topics
  • Technology
  • body bias
  • source bias
  • standby current
  • static noise margin

Location

  • San Jose, CA

Digital Object Identifier (DOI)

International Standard Book Number (ISBN) 13

Conference

  • 10th International Symposium on Quality Electronic Design

publisher

  • IEEE

start page

  • 471

end page

  • +