A novel low cost 65nm CMOS process architecture with self aligned isolation and W cladded source/drain Conference

Blosse, A, Rarnkumar, K, Gopalan, P et al. (2004). A novel low cost 65nm CMOS process architecture with self aligned isolation and W cladded source/drain . 669-672. 10.1109/IEDM.2004.1419256

cited authors

  • Blosse, A; Rarnkumar, K; Gopalan, P; Hsu, CT; Narayanan, S; Narasimhan, G; Gettle, R; Kapre, R; Sharifzadeh, S

authors

date/time interval

  • December 13, 2004 -

publication date

  • January 1, 2004

webpage

keywords

  • Engineering
  • Engineering, Electrical & Electronic
  • Materials Science
  • Materials Science, Multidisciplinary
  • Physical Sciences
  • Physics
  • Physics, Condensed Matter
  • Science & Technology
  • Technology

Location

  • San Francisco, CA

Digital Object Identifier (DOI)

International Standard Book Number (ISBN) 10

Conference

  • 50th IEEE International Electron Devices Meeting

publisher

  • IEEE

start page

  • 669

end page

  • 672