High-level synthesis for large bit-width multipliers on FPGAs: A case study Conference

Quan, G, Davis, JP, Devarkal, S et al. (2005). High-level synthesis for large bit-width multipliers on FPGAs: A case study . 213-218.

cited authors

  • Quan, G; Davis, JP; Devarkal, S; Buell, DA

authors

date/time interval

  • September 18, 2005 -

publication date

  • January 1, 2005

keywords

  • Computer Science
  • Computer Science, Hardware & Architecture
  • Computer Science, Software Engineering
  • FPGA devices
  • Science & Technology
  • Technology
  • design exploration
  • high level synthesis
  • large-scale integer multipliers
  • reconfigurable computing

Location

  • NJ, Jersey City

International Standard Book Number (ISBN) 10

Conference

  • International Conference on Hardware/Software Codesign and System Synthesis

publisher

  • ASSOC COMPUTING MACHINERY

start page

  • 213

end page

  • 218