In this highly-technical, industrial driven market, companies are striving to sustain their competitive edge by researching and implementing methodologies which reduce development time and introduce productlines to consumers quickly and cost effectively. From a Hardware Architect's perspective, designing realtime hardware involves various stages of modeling. A new, emerging hardware description language (HDL) called SystemC is currently capturing industries attention since it introduces a broad range of abstract level model techniques under one platform. SystemC is also an open-source language. Consumers are capable of stimulating various levels of modeling from the transaction level (TL) to the Register Transfer Level (RTL). Companies are investigating these potential strategic changes of functional verification stages in order to compress development time. In order to meet future demand, Hardware EDA Vendors such as Synopsys and Mentor Graphics have introduced new EDA tools that support SystemC synthesis. This introduces a new paradigm for future change of the support and functional verification stages of product development. In today's market, co-hardware/software systems are being developed to determine the best-fit location of these modules. With this research premise, this study introduces a new implementation of a Hardware SystemC Register Transfer Level Model of a 2D-Discrete Cosine Transform using Distributed Arithmetic Algorithm. This model is integrated into an image and video compression system.
